The present invention is related to a semiconductor integrated circuit (IC) device having a sense amplifier circuit amplifying a very weak signal. In particular, the present invention relates to an improvement of the precision and increase in the operation speed of a semiconductor IC device associated with variations in characteristics between constituent elements thereof because the device is manufactured with a pattern of a fine structure leading to difficulty of dimension control in fabrication.
Heretofore, an example of a semiconductor memory device which includes sense amplifiers for amplifying very weak signals read from memory cells fabricated with a pattern of a fine lines has been described in a chapter "MOS Dynamic RAM (pp. 486-499)" of the "LSI Handbook", IEICE Japan, the Ohm-Sha Ltd. (1984).
Moreover, a DRAM including sense amplifier circuits constituted with CMOS transistors has been commonly used. FIG. 23 shows the constitution of such a DRAM. In this connection, a complementary signal marked with an over-line in the drawings will be represented as a signal preceded by a slant (/). Furthermore, unless otherwise specified, a signal designating a terminal name also indicates a wiring name and a line name, and in a case of a signal of a power source, a voltage value thereof is also designated.
The system of FIG. 23 includes a memory cell MCl, a word line W1, data lines D1 and /D1, a data line amplifier RA as a sense amplifier, signals PP and PN controlling the data line amplifier circuit RA, a precharge circuit PCC, and a signal PC controlling the precharge circuit PCC. MOS transistors M1 and M2 generate across output signal lines RO and /RO a signal current difference associated with a very-weak signal voltage difference developed between the data lines D1 and /D1. RM denotes a read switching circuit and YSR designates a signal controlling the read switching circuit RM. Moreover, WI and /WI are write signal lines, WM stands for a write switching circuit, and YSW indicates a signal controlling the write switching circuit WM.
In a read operation of the DRAM constructed as shown in FIG. 23, the input terminals D1 and /D1 of the data line amplifier circuit RA are precharged as shown in FIG. 24 by the precharge circuit PCC to a precharge potential of HVD, and then the PC is set to a lower level, thereby establishing a floating state of the data lines D1 and /D1.
Subsequently, when the word line W1 is set to a high level, a signal is read from the memory cell MCl onto the data line D1. This slightly varies the potential of the data line D1. A difference between the potential of D1 and that of /D1 retained at HVD is sensed and is amplified by the data line amplifier RA.